STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet - Page 24
STC4130-I
Manufacturer Part Number
STC4130-I
Description
Synchronous Clock for SETS
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.STC4130-I.pdf
(44 pages)
- Current page: 24 of 44
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Multiplex Bus Mode
In multiplex bus mode, the device can interface with microprocessors which share the address and data on the
same bus signals. The BUS_ALE, BUS_CS, BUS_WRB, BUS_RDB, BUS_AD(7-0), and BUS_RDY pins are
used, corresponding to ALE, CS, WRB, RDB, AD, and RDY, respectively.
Multiplex Bus Timing
WRB
ALE
RDB
RDY
AD
CS
t
t
ALE
ADs
Symbol
t
t
t
t
RDYd1
RDYd2
t
t
t
t
t
RDYh
t
ALEd
t
t
t
t
RDB
RDY
ALE
ADs
ADh
CSs
CSh
CSd
Dd1
Dh2
Address
© Copyright 2006 The Connor-Winfield Corp.
t
ADh
ALE high time
ALE falling edge to RDB low
Address setup time
Address hold time
Read setup time
Read time
CS hold time
CS delay for multiple read/writes
Data valid delay from RDB low
Data high-z from RDB high
CS low to RDY active
RDB low to RDY low
RDY low time
Read hold after RDY high
t
ALEd
t
RDYd1
t
CSs
Figure 15: Multiplex Bus Read Timing
Table 10: Multiplex Bus Read Timing
Data Sheet #: TM084
t
t
RDYd2
Dd1
Description
t
RDY
t
t
CSd
RDB
Data
All Rights Reserved
t
RDYh
Page 24 of 44
Synchronous Clock for SETS
t
Dh2
t
CSh
Min
10
10
10
40
50
50
0
0
0
0
Specifications subject to change without notice
t
RDYd3
Max
50
10
13
40
Rev: P02
Unit
STC4130
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Data Sheet
Date: 12/5/06
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