STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet - Page 37

• Manufacturer Part Number: STC4130-I
• Description: Synchronous Clock for SETS
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

SYNC: Indicates synchronization has been achieved
LOS: Loss of signal
LOL: Loss of lock
OOP: Out of pull-in range
LHC: Long Term History Complete
LHA: Long Term History Available
T4_Accu_Flush, 0x55 (W)
Writing to this register will perform a flush of the accumulated history. The value of bit zero determines which
histories are flushed. Bit 0 = 0, Flush T4 current history only; bit 0 = 1, flush all T4 histories.
CLK0_Sel, 0x56 (R/W)
Enables or disables the 155.52MHz CLK0 output.
Default vale: 0.
CLK1_Sel, 0x57 (R/W)
Selects or disables the CLK1 output.
Default value: 1.
Address
Address
Address
0x55
0x56
0x57
Bit7
Bit7
Bit7
© Copyright 2006 The Connor-Winfield Corp.
Bit6
Bit6
Bit6
Data Sheet #: TM084
0x57, bits 1 ~ 0
Bit5
Bit5
Bit5
Not used
0
1
2
3
Not used
Not used
Bit4
Bit4
Bit4
CLK1 output
All Rights Reserved
19.44MHz
38.88MHz
77.76MHz
Disabled
Page 37 of 44
Bit3
Bit3
Bit3
Synchronous Clock for SETS
Specifications subject to change without notice
Bit2
Bit2
Bit2
Rev: P02
STC4130
Data Sheet
Bit1
Bit1
Bit1
CLK1 Select
Date: 12/5/06
0=Disable
1=Enable
HO flush
Bit0
Bit0
Bit0