STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet - Page 30

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STC4130-I

Manufacturer Part Number
STC4130-I
Description
Synchronous Clock for SETS
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
Reference activity indicator, 0 = no activity, 1 = activity.
Refs_Qual, 0x1a (R)
Reference qualification indicator, 0 = not qualified, 1 = qualified.
T0_Control_Mode, 0x1c (R/W)
Mode control bits for T0.
Bit 0: 0 = Arbitrary (use initial phase), 1 = Phase align
Bit 2, Accu_Usage: 0 = Device calculated long term history (LTH) is used; 1 = User supplied history is used.
Bit 5, OOP: In manual mode, when the selected active reference is out of the pull-in range, as specified in reg-
ister Disqualification_Range, 0x10, OOP will determine if the reference is to be followed, 0 = Don’t follow, 1 =
Follow.
Default value: 0.
T0_Bandwidth, 0x1d (R/W)
Sets the T0 bandwidth:
Address
Address
Address
0x1a
0x1b
0x1c
0x1d
Ref 8
Bit7
Bit7
Bit7
Not used
© Copyright 2006 The Connor-Winfield Corp.
Not used
Ref 7
Bit6
Bit6
Bit6
Not used
OOP: Out
of Pull-in
range:
0=Follow
1=Don’t fol-
low
Data Sheet #: TM084
0x1d, bits 4 ~ 0
Ref 6
Bit5
Bit5
Bit5
0
1
2
3
4
5
6
7
8
0=Manual
Manual/
1=Auto
Ref 5
Auto
Bit4
Bit4
Bit4
Bandwidth, Hz
All Rights Reserved
0.37
107
5.9
2.9
1.5
.73
50
24
12
Revertive
1=Rever-
revertive
Page 30 of 44
0=Non-
Ref 12
Ref 4
Bit3
Bit3
Bit3
tive
Synchronous Clock for SETS
Specifications subject to change without notice
Accu_Usage
Ref 11
1=User
0=LTH
Ref 3
Bit2
Bit2
Bit2
Rev: P02
STC4130
Ref 10
Ref 2
Data Sheet
Bit1
Bit1
Bit1
Date: 12/5/06
Align Mode
0=Arbitrary
1=Align
Phase
Ref 1
Ref 9
Bit0
Bit0
Bit0

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