HYB25DC512800CF-5 QIMONDA [Qimonda AG], HYB25DC512800CF-5 Datasheet - Page 29

• Manufacturer Part Number: HYB25DC512800CF-5
• Description: 512-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

4.2.1
Legend: A = Activate, R = Read, RA = Read with Autoprecharge, P = Precharge, N = NOP or DESELECT
I
1. General test condition
2. Timing patterns
I
1. General test condition
2. Timing patterns
Rev. 1.3, 2006-12
03292006-W2FE-ELDX
DD1
DD7
a) Only one bank is accessed with
b) Burst Mode, Address and Control inputs are changing once per NOP and DESELECT cycle.
c) 50% of data changing at every transfer
d)
a) DDR333B (166 MHz, CL = 2.5):
b) DDR400B (200 MHz, CL = 3):
a) Four banks are being interleaved with
b) Burst Mode, Address and Control inputs on NOP edge are not changing.
c) 50% of data changing at every transfer
d)
a) DDR333B (166 MHz, CL = 2.5):
b) DDR400B (200 MHz, CL = 3):
: Operating Current: One Bank Operation
: Operating Current: Four Bank Operation
I
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing
Setup:A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address changing
I
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing with random address
OUT
OUT
= 0 mA.
= 0 mA.
Current Measurement Conditions
t
t
CK
CK
t
t
t
RC,MIN
CK
CK
= 5 ns, BL = 4,
= 5 ns, BL = 4,
= 6 ns, BL = 4,
= 6 ns, BL = 4,
t
.
RCMIN
.
t
t
RCD
RRD
t
t
RCD
RRD
= 3 ×
= 2 ×
29
= 3 ×
= 2 ×
t
t
CK
CK
t
t
CK
CK
,
,
t
t
,
,
RC
RCD
t
t
RC
RCD
= 11 ×
= 3 *×
= 9 ×
= 3 ×
t
t
CK
t
CK
CK
t
CK
,
512-Mbit Double-Data-Rate SDRAM
,
,
t
,
t
RAS
t
RAS
RAS
t
RAS
= 8 ×
= 5 ×
= 8 ×
= 5 ×
HYB25DC512[800/160]C[E/F]
t
t
CK
t
CK
CK
t
CK
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