HYB25DC512800CF-5 QIMONDA [Qimonda AG], HYB25DC512800CF-5 Datasheet - Page 26

• Manufacturer Part Number: HYB25DC512800CF-5
• Description: 512-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) For each of the terms, if not already an integer, round to the next highest integer.
7)
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
Rev. 1.3, 2006-12
03292006-W2FE-ELDX
Parameter
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command
delay
Exit self-refresh to non-read
command
Exit self-refresh to read command
Parameter
Operating Current: one bank; active/ precharge;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤
Precharge Floating Standby Current: CS ≥ V
CKE ≥
and DM.
Precharge Quiet Standby Current: CS ≥ V
control inputs stable at ≥
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V
other than CK/CK, is
t
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
between
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on
performance (bus turnaround) degrades accordingly.
HZ
t
and
DQSS
V
IHMIN
ILMAX
T
t
.
A
LZ
V
≤ 70 °C;
IH(ac)
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
;
;
t
t
CK
CK
and
=
=
t
t
V
CKMIN
CKMIN
V
DDQ
V
IL(ac)
REF
= 2.5 V ± 0.2 V,
, address and other control inputs changing once per clock cycle,
;
V
.
. CK/CK slew rate are ≥ 1.0 V/ns.
V
IHMIN
IN
=
or ≤
V
REF
Symbol
t
t
t
t
t
t
WPRES
WPST
WR
WTR
XSNR
XSRD
V
for DQ, DQS and DM.
ILMAX
V
V
REF
DD
stabilizes.
;
= +2.5 V ± 0.2 V (DDR333);
V
IHMIN
IN
–5
0
0.40
15
2
75
200
DDR400B
Min.
=
IHMIN
V
, all banks idle; CKE ≥ V
REF
t
RC
, all banks idle;
for DQ, DQS and DM.
=
t
RCMIN
26
;
t
CK
Max.
—
0.60
—
—
—
—
=
t
V
CKMIN
DDQ
IHMIN
= 2.6 V ± 0.1 V,
;
–6
DDR333
Min.
0
0.40
15
1
75
200
t
CK
;
is equal to the actual system clock cycle time.
t
CK
=
512-Mbit Double-Data-Rate SDRAM
t
CKMIN
V
V
ILMAX
DD
V
, address and other
IN
HYB25DC512[800/160]C[E/F]
= +2.6 V ± 0.1 V (DDR400)
Max.
—
0.60
—
—
—
—
;
=
t
CK
V
REF
=
t
CKMIN
for DQ, DQS
Unit Note/ Test
ns
t
ns
t
ns
t
Internet Data Sheet
CK
CK
CK
I
TABLE 20
DD
Condition
2)3)4)5)10)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
V
TT
Conditions
.
Symbol
I
I
I
I
I
I
DD0
DD1
DD2P
DD2F
DD2Q
DD3P
1)