HYB25DC512800CF-5 QIMONDA [Qimonda AG], HYB25DC512800CF-5 Datasheet - Page 16

• Manufacturer Part Number: HYB25DC512800CF-5
• Description: 512-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see
Rev. 1.3, 2006-12
03292006-W2FE-ELDX
Current State
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
Current State
Any
Idle
Row Active
Read (Auto
Precharge
Disabled)
Write (Auto
Precharge
Disabled)
V
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
was self refresh).
REF
must be maintained during Self Refresh operation
CS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
CKE n-1
Previous
Cycle
L
L
L
L
H
H
H
H
RAS CAS WE
X
H
L
L
L
H
H
L
H
L
H
H
H
L
CKEn
Current
Cycle
L
H
L
H
L
L
L
H
X
H
H
L
L
L
L
H
L
H
H
L
L
H
X
H
H
H
L
H
L
L
H
L
L
H
L
L
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Command n
X
Deselect or NOP
X
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
See
Command
Deselect
No Operation
Active
AUTO REFRESH
MODE REGISTER
SET
Read
Write
Precharge
Read
Precharge
BURST
TERMINATE
Read
Write
Precharge
Table 12
16
Table 11
Action
NOP. Continue previous operation.
NOP. Continue previous operation.
Select and activate row
–
–
Select column and start Read burst
Select column and start Write burst
Deactivate row in bank(s)
Select column and start new Read burst
Truncate Read burst, start Precharge
BURST TERMINATE
Select column and start Read burst
Select column and start Write burst
Truncate Write burst, start Precharge
and after
Exit Power-Down
Active Power-Down Entry
Action n
Maintain Self-Refresh
Exit Self-Refresh
Maintain Power-Down
Precharge Power-Down Entry
Self Refresh Entry
–
t
XSNR
Truth Table 2: Clock Enable (CKE)
512-Mbit Double-Data-Rate SDRAM
/
t
XSRD
HYB25DC512[800/160]C[E/F]
has been met (if the previous state
t
XSNR
) period. A minimum of 200
Internet Data Sheet
TABLE 11
TABLE 12
Note
1)2)3)4)5)6)
1) to 6)
1) to 6)
1) to 7)
1) to 7)
1) to 6), 8)
1) to 6), 8)
1) to 6), 9)
1) to 6), 8)
1) to 6), 9)
1) to 6), 10)
1) to 6), 8), 11)
1) to 6), 8)
1) to 6), 9), 11)
Note
1)
2)