HYB25DC512800CF-5 QIMONDA [Qimonda AG], HYB25DC512800CF-5 Datasheet - Page 23

• Manufacturer Part Number: HYB25DC512800CF-5
• Description: 512-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

4.2
Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions,
Specifications and Conditions, and Electrical Characteristics and AC Timing.
Notes
1. All voltages referenced to
2. Tests for AC timing,
3.
4. AC timing and
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SDRAM Slew
Rev. 1.3, 2006-12
03292006-W2FE-ELDX
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
Figure 3
to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line
terminated at the tester electronics).
to
under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between
a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level).
Rate Standards, Overshoot & Undershoot specification and Clamp
for DDR components.
V
REF
(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended
I
DD
AC Characteristics
tests may use a
I
DD
, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
V
SS
Output
(
.
V
OUT
V
IL
)
to
V
IH
swing of up to 1.5 V in the test environment, but input timing is still referenced
AC Output Load Circuit Diagram / Timing Reference Load
V
TT
30 pF
23
50
Timing Reference Point
V
-
I
characteristics see the latest Industry specification
512-Mbit Double-Data-Rate SDRAM
HYB25DC512[800/160]C[E/F]
Internet Data Sheet
V
FIGURE 3
IL(AC)
and
V
IH(AC)
I
DD
.