HYB25DC512800CF-5 QIMONDA [Qimonda AG], HYB25DC512800CF-5 Datasheet - Page 21

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HYB25DC512800CF-5

Manufacturer Part Number
HYB25DC512800CF-5
Description
512-Mbit Double-Data-Rate SDRAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet

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Part Number:
HYB25DC512800CF-5
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1) These values are guaranteed by design and are tested on a sample base only.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
1) 0 °C ≤ T
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions,
4) Peak to peak AC noise on
Rev. 1.3, 2006-12
03292006-W2FE-ELDX
Parameter
Input/Output Capacitance: DQ, DQS, DM
Delta Input/Output Capacitance: DQ, DQS,
DM
Parameter
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
Supply Voltage, I/O Supply
Voltage
Input Reference Voltage
I/O Termination Voltage
(System)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
Input Voltage Level, CK and
CK Inputs
Input Differential Voltage,
CK and CK Inputs
VI-Matching Pull-up Current
to Pull-down Current
Input Leakage Current
Output Leakage Current
Output High Current, Normal
Strength Driver
Output Low Current, Normal
Strength Driver
V
board level.
OUT(DC)
A
=
≤ 70 °C; V
V
DDQ
/2,
V
OUT
DDQ
V
DDQ
(Peak to Peak) 0.2 V. Unused pins are tied to ground.
= 2.5 V ± 0.2 V, V
must be less than or equal to
V
REF
Symbol
V
V
V
V
V
V
V
V
V
V
V
V
I
I
I
I
I
OZ
OH
OL
may not exceed ± 2%
DD
DD
DDQ
DDQ
SS
REF
TT
IH(DC)
IL(DC)
IN(DC)
ID(DC)
I
Ratio
,
V
SSQ
DD
= +2.5 V ± 0.2 V;
Min.
2.3
2.5
2.3
2.5
0
0.49 × V
V
V
–0.3
–0.3
0.36
0.71
–2
–5
16.2
REF
REF
Symbol
C
C
+ 0.15
IO
dIO
– 0.04
V
DDQ
REF.DC
V
DD
.
Electrical Characteristics and DC Operating Conditions
.
Typ.
2.5
2.6
2.5
2.6
0.5 × V
V
Values
REF
21
Min.
3.5
4.0
is also expected to track noise variations in
DDQ
Max.
2.7
2.7
2.7
2.7
0
0.51 × V
V
V
V
V
V
1.4
2
5
–16.2
Typ.
Values
REF
DDQ
REF
DDQ
DDQ
V
DDQ
+ 0.04
– 0.15
+ 0.3
+ 0.3
+ 0.6
=
DDQ
V
Max.
4.5
5.0
0.5
DD
512-Mbit Double-Data-Rate SDRAM
= 2.5 V ± 0.2 V, f = 100 MHz, T
Unit Note
V
V
V
V
V
V
V
V
V
V
V
µA
µA
mA
mA
HYB25DC512[800/160]C[E/F]
pF
Unit
pF
pF
f
f
f
f
4)
5)
6)
6)
6)
6)7)
8)
Any input 0 V ≤ V
other pins not under test = 0 V
DQs are disabled; 0 V ≤ V
V
V
V
CK
CK
CK
CK
DDQ
OUT
OUT
≤ 166 MHz
> 166 MHz
≤ 166 MHz
> 166 MHz
1)
=
= 0.35 V
9)
/Test Condition
1.95 V
Internet Data Sheet
V
Note/
Test Condition
TFBGA
TSOPII
1)
DDQ
.
TABLE 17
3)
2)
2)3)
IN
1)2)
1)2)
A
≤ V
= 25 °C,
DD
; All
OUT
9)

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