NAND04GA3C2A STMICROELECTRONICS [STMicroelectronics], NAND04GA3C2A Datasheet - Page 22

• Manufacturer Part Number: NAND04GA3C2A
• Description: 4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

6 Device operations
6.6
6.7
Figure 8.
22/51
RB
I/O
Sequential Input
To input data sequentially the addresses must be sequential and remain in one block.
For Sequential Input each Page Program operation comprises five steps:
1.
2.
3.
4.
5.
Random Data input
During a Sequential Input operation, the next sequential address to be programmed can be
replaced by a random address, by issuing a Random Data Input command. The following
two steps are required to issue the command:
1.
2.
Random Data Input can be repeated as often as required in any given page.
Once the program operation has started the Status Register can be read using the Read
Status Register command. During program operations the Status Register will only flag
errors for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands will be
accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in Read Status Register mode until another valid command is written to
the Command Interface.
Page Program Operation
Page Program
Setup Code
One bus cycle is required to setup the Page Program (Sequential Input) command (see
Table
Five bus cycles are then required to input the program address (refer to
The data is then loaded into the Data Registers.
One bus cycle is required to issue the Page Program confirm command to start the
P/E/R Controller. The P/E/R will only start if the data has been loaded in step 3.
The P/E/R Controller then programs the data into the array.
One bus cycle is required to setup the Random Data Input command (see
Two bus cycles are then required to input the new column address (refer to
80h
8).
Address Inputs
Data Input
(Program Busy time)
Confirm
NAND04GA3C2A, NAND04GW3C2A
Code
10h
tBLBH2
Busy
Read Status Register
70h
Table
Table
Table
SR0
6).
ai08659
8).
6).