NAND04GA3C2A STMICROELECTRONICS [STMicroelectronics], NAND04GA3C2A Datasheet - Page 20

• Manufacturer Part Number: NAND04GA3C2A
• Description: 4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

6 Device operations
Figure 6.
6.4
20/51
RB
I/O
R
Row Add 1,2,3
Code
000h
Cmd
Random Data Output
Cache Read
The Cache Read operation is used to improve the read throughput by reading data using
the Cache Register. As soon as the user starts to read one page, the device automatically
loads the next page into the Cache Register.
An Cache Read operation consists of three steps (see
1.
2.
3.
The Start Address must be at the beginning of a page (Column Address = 000h, see
7.). This allows the data to be output uninterrupted after the latency time (t
Figure 7.
5 Add cycles
Address
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command).
Five bus cycles are then required to input the Start Address (refer to
One bus cycle is required to issue the Cache Read confirm command to start the P/E/R
Controller.
Inputs
(Read Busy time)
Col Add 1,2
tBLBH1
Code
30h
Main Area
Cmd
Busy
Data Output
Spare
Area
Code
Cmd
05h
Col Add 1,2
2Add cycles
Address
Inputs
NAND04GA3C2A, NAND04GW3C2A
Table
Code
E0h
Cmd
Main Area
8):
Data Output
Spare
Area
Table
BLBH1
6).
), see
ai08658b
Table