NAND04GA3C2A STMICROELECTRONICS [STMicroelectronics], NAND04GA3C2A Datasheet - Page 17

• Manufacturer Part Number: NAND04GA3C2A
• Description: 4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND04GA3C2A, NAND04GW3C2A
5
Table 8.
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are
2. For consecutive read operations the 00h command does not need to be repeated.
3. Only when a Cache Read operation is ongoing.
Read
Random Data Output
Cache Read
Exit Cache Read
Page Program
(Sequential Input default)
Random Data Input
Block Erase
Reset
Read Electronic Signature
Read Status Register
not shown.
Command
Command Set
All bus write operations to the device are interpreted by the Command Interface. The
Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is high. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The Commands are summarized in
Commands
1
st
00h
CYCLE
FFh
05h
00h
34h
80h
85h
60h
90h
70h
(2)
Table 8:
2
Bus Write Operations
nd
D0h
E0h
CYCLE
30h
31h
10h
–
–
–
–
–
Commands.
3
rd
CYCLE
–
–
–
–
–
–
–
–
–
–
(1)
4
th
CYCLE
–
–
–
–
–
–
–
–
–
–
5 Command Set
during busy
Commands
accepted
Yes
Yes
Yes
(3)
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