HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 91

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

5.1
5.1.1
Exception handling is started by four sources: resets, address errors, interrupts and instructions and
have the priority, as shown in table 5.1. When several exceptions are detected at once, they are
processed according to the priority.
Table 5.1
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
Exception
Reset
Interrupt
Address error
Instruction
Address error
Interrupt
2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,
Overview
Types of Exception Handling and Priority
BRAF.
TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.
Types of Exceptions and Priority
Exception Source
Power-on reset
H-UDI reset
User break (break before instruction execution)
CPU address error (instruction fetch)
General illegal instructions (undefined code)
Illegal slot instruction (undefined code placed immediately after a
delayed branch instruction*
Trap instruction (TRAPA instruction)
CPU address error (data access)
User break (break after instruction execution or operand break)
NMI
H-UDI
IRQ
On-chip
peripheral
modules:
Section 5 Exception Handling
Watchdog timer (WDT)
Compare match timer 0 and 1 (CMT0 and CMT1)
Serial communication interface with FIFO (SCIF0,
SCIF1, and SCIF2)
Host interface (HIF)
1
or instruction that changes the PC value*
Rev. 4.00 Sep. 13, 2007 Page 65 of 502
Section 5 Exception Handling
REJ09B0239-0400
2
)
Priority
High
Low