HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 125

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

6.4.2
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules.
Since a different interrupt vector is allocated to each interrupt source, the exception handling
routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can
be allocated to individual on-chip peripheral modules in interrupt priority registers C to E (IPRC
to IPRE). On-chip peripheral module interrupt exception handling sets the interrupt mask level
bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module
interrupt that was accepted.
6.4.3
A user break interrupt has a priority level of 15, and occurs when the break condition set in the
user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are
held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3
to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see
section 16, User Break Controller (UBC).
IRQn pins
(Acceptance of IRQn interrupt/
writing 0 after reading IRQnF = 1)
On-Chip Peripheral Module Interrupts
User Break Interrupt
Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control
detection
detection
RESIRQn
Level
Edge
IRQSR.IRQnL
S
R
IRQCR.IRQn1S
IRQCR.IRQn0S
Q
Rev. 4.00 Sep. 13, 2007 Page 99 of 502
IRQSR.IRQnF
Section 6 Interrupt Controller (INTC)
n = 7 to 0
REJ09B0239-0400
CPU interrupt
request