HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 204

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Bus State Controller (BSC)
Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus
cycle execution, the refresh cycle must wait for the bus cycle to be completed.
If a new refresh request occurs while the previous refresh request is not performed, the previous
refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the
bus busy must be prevented.
Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed
after turning the power on. To perform synchronous DRAM initialization correctly, the BSC
registers must first be set, followed by writing to the synchronous DRAM mode register. When
writing to the synchronous DRAM mode register, the address signal value at that time is latched
by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, write to
the address of X + (H'F8FD5000) in words. In this operation, the data is ignored. To set burst
read/single write, burst read/burst write, CAS latency 2 to 3, wrap type = sequential, and burst
length 1 supported by the LSI, arbitrary data is written to the addresses shown in table 7.17 in
bytes. In this case, 0s are output at the external address pins of A12 or later.
Rev. 4.00 Sep. 13, 2007 Page 178 of 502
REJ09B0239-0400
D15 to D0
A25 to A0
Note: * Address pin to be connected to pin A10 of SDRAM.
RD/WR
DQMxx
CKIO
A11*
CKE
RAS
CAS
CSn
BS
Tp
Tpw
Figure 7.24 Self-Refreshing Timing
Trr
Hi-z
Trc
Trc
Trc
Trc
Trc