HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 77

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

3.1
• Capacity: 16 kbytes
• Structure: Instructions/data unified, 4-way set associative
• Line size: 16 bytes
• Number of entries: 256 entries/way in 4-kbyte mode
• Write method: Write-back/write-through is selectable
• Replacement method: Least-recently-used (LRU) algorithm
3.1.1
The cache holds both instructions and data and employs a 4-way set associative system. It is
composed of four ways (banks), and each of which is divided into an address section and a data
section. Each of the address and data sections is divided into 256 entries. The data of an entry is
called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes
(16 bytes × 256 entries), with a total of 16 kbytes in the cache (4 ways).
Figure 3.1 shows the cache structure.
Entry 255
Features
Cache Structure
Entry 0
Entry 1
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24 (1 + 1 + 22) bits
V U Tag address
Address array (ways 0 to 3)
Figure 3.1 Cache Structure
Section 3 Cache
255
0
1
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LW0
LW0 to LW3: Longword data 0 to 3
128 (32 × 4) bits
LW1
LW2
Data array (ways 0 to 3)
Rev. 4.00 Sep. 13, 2007 Page 51 of 502
LW3
255
0
1
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REJ09B0239-0400
Section 3 Cache
LRU
6 bits