HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 409

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

16.2.7
BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data
specified by BDRB.
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
16.2.8
Break bus cycle register B (BBRB) is a 16-bit readable/writable register, which specifies (1) L bus
cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in
the break conditions of channel B.
Bit
31 to 0
Bit
15 to 8
2. When the byte size is selected as a break condition, the same byte data must be set in
Break Data Mask Register B (BDMRB)
Break Bus Cycle Register B (BBRB)
Bit Name
BDMB31 to
BDMB 0
Bit Name
—
bits 15−8 and 7−0 in BDMRB as the break mask data.
Initial
Value
All 0
Initial
Value
All 0
R/W
R
R/W
R/W
Description
Break Data Mask B
Specifies bits masked in the break data of channel B
specified by BDRB (BDB31 to BDB0).
0: Break data BDBn of channel B is included in the
1: Break data BDBn of channel B is masked and is not
Note: n = 31 to 0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
break condition
included in the break condition
Rev. 4.00 Sep. 13, 2007 Page 383 of 502
Section 16 User Break Controller (UBC)
REJ09B0239-0400