HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 79

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

3.1.2
A 4-G byte address space is divided into five areas with the architecture of this LSI. The cache
access methods can be specified for each area. Table 3.2 lists the correspondence between the
divided areas and cache.
Table 3.2
Address
H'00000000 to H'7FFFFFFF
H'80000000 to H'9FFFFFFF
H'A0000000 to H'BFFFFFFF
H'C0000000 to H'DFFFFFFF
H'E0000000 to H'FFFFFFFF
Divided Areas and Cache
Correspondence between Divided Areas and Cache
Area
P0
P1
P2
P3
P4
Cacheable
Cacheable
Cacheable
Non cacheable
Cacheable
Non cacheable (internal I/O) 
Rev. 4.00 Sep. 13, 2007 Page 53 of 502
Cache Operating
Control
WT bit in CCR1
CB bit in CCR1

WT bit in CCR1
REJ09B0239-0400
Section 3 Cache