HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 192

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HD6417606

Manufacturer Part Number
HD6417606
Description
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 7 Bus State Controller (BSC)
Single Read: A read access ends in one cycle when data exists in non-cacheable area and the data
bus width is larger than or equal to access size. Since the burst length is set to 1 in synchronous
DRAM burst read/single write mode, only the required data is output. Consequently, no
unnecessary bus cycles are generated even when a cache-through area is accessed.
Figure 7.14 shows the single read basic timing.
Rev. 4.00 Sep. 13, 2007 Page 166 of 502
REJ09B0239-0400
Figure 7.14 Basic Timing for Single Read (Auto Precharge)
D15 to D0
A25 to A0
Note: * Address pin to be connected to pin A10 of SDRAM.
RD/WR
DQMxx
CKIO
A11*
RAS
CAS
CSn
BS
Tr
Tc1
Td1
Tde
Tap

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