HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 570

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14. I
14.4.9
The states on the SCL and SDA pins are fetched internally via the noise canceller. Figure 14.28 is
a block diagram of the noise canceller.
The noise canceller consists of a 2-stage latch circuit and match-detection circuit, which are
connected in series. The input signal on the SCL pin (or on the SDA pin) is sampled on the system
clock; when the two latch outputs match, the given level is then sent to the next stage. If the two
values do not match, the existing value is maintained.
14.4.10 Initialization of Internal State
This IIC module has a function for forcible initialization of its internal state if a deadlock occurs
during communication.
Initialization is executed by clearing ICE bit.
Rev.4.00 Mar. 27, 2008 Page 526 of 882
REJ09B0108-0400
SCL input signal or
SDA input signal
2
C Bus Interface (IIC) Option
Sampling clock
Noise Canceller
Figure 14.28 Block Diagram of the Noise Canceller
System clock period
D
Sampling clock
Latch
C
Q
D
Latch
C
Q
Match-detection
circuit
Internal SCL signal or
Internal SDA signal