HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 370

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.
11.7.8
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 11.76 shows the timing in this case.
Rev.4.00 Mar. 27, 2008 Page 326 of 882
REJ09B0108-0400
Multi-Function Timer Pulse Unit (MTU)
Figure 11.75
Contention between TGR Read and Input Capture
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
TGR
Pφ
Figure 11.76
Pφ
Address
Read signal
Input capture
signal
TGR
Internal data
bus
Contention between Buffer Register Write and Compare Match
Contention between TGR Read and Input Capture
(Channels 3 and 4)
X
N
TGR read cycle
TGR write cycle
Buffer register
T1
TGR address
T1
address
M
T2
T2
M
M
N
Buffer register write data