HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 255

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

With indirect addressing, the first executed data read from the address established in SAR_3
always results in a longword size transfer regardless of the TS0, TS1 bit designations for transfer
data size. However, the transfer source address fixed and increment or decrement designations are
as according to the SM0, SM1 bits. Consequently, despite the fact that the transfer data size
designation is byte in this example, the SAR_3 value at the end of one transfer is H'00400004. The
write operation is exactly the same as an ordinary dual address transfer write operation.
10.6
1. The DMA operation register (DMAOR) can be accessed only in word (16-bit) units. The other
2. When rewriting the RS0 to RS3 bits of CHCR_0 to CHCR_3, first clear the DE bit to 0 (set the
3. When an NMI interrupt is input, the NMIF bit of the DMAOR is set even when the DMAC is
4. Set the DME bit of the DMAOR to 0 and make certain that any DMAC received transfer
5. Do not access the DMAC, DTC, BSC, or UBC on-chip peripheral modules from the DMAC.
6. When activating the DMAC, do the CHCR or DMAOR setting as the final step. There are
7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write a 0 to
8. Designate burst mode as the transfer mode when using the address reload function. There are
9. Designate a multiple of four for the DMATCR value when using the address reload function.
10. When detecting external requests by falling edge, maintain the external request pin at high
11. When operating in single address mode, establish an external address as the address. There are
12. Do not access DMAC register empty addresses (H'FFFF86B2 to H'FFFF86BF). Operation
registers can be accessed in word (16-bit) or longword (32-bit) units.
DE bit to 0 before doing rewrites with CHCR).
not operating.
request processing has been completed before entering standby mode.
instances where abnormal operation will result if any other registers are established last.
the DMATCR, even when executing the maximum number of transfers on the same channel.
There are instances where abnormal operation will result if this is not done.
instances where abnormal operation will result in cycle steal mode.
There are instances where abnormal operation will result if anything else is designated.
level when performing the DMAC establishment.
instances where abnormal operation will result if an internal address is established.
cannot be guaranteed when empty addresses are accessed.
Usage Notes
10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 211 of 882
REJ09B0108-0400