HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 117

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.6
When an address error or interrupt is generated directly after a delayed branch instruction or
interrupt-disabled instruction, it is sometimes not accepted immediately but stored instead, as
shown in table 5.10. In this case, it will be accepted when an instruction that can accept the
exception is decoded.
Table 5.10 Generation of Exception Sources Immediately after Delayed Branch Instruction
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
5.6.1
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,
neither address errors nor interrupts are accepted. The delayed branch instruction and the
instruction placed immediately after it (delay slot) are always executed consecutively, so no
exception processing occurs during this period.
5.6.2
When an instruction placed immediately after an interrupt-disabled instruction is decoded,
interrupts are not accepted. Address errors can be accepted.
Point of Occurrence
Immediately after a delayed branch instruction*
Immediately after an interrupt-disabled instruction*
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L
Cases when Exception Sources Are not Accepted
Immediately after Delayed Branch Instruction
Immediately after Interrupt-Disabled Instruction
BRAF
or Interrupt-Disabled Instruction
1
2
Rev.4.00 Mar. 27, 2008 Page 73 of 882
Address Error
Not accepted
Accepted
Exception Source
5. Exception Processing
Interrupt
Not accepted
Not accepted
REJ09B0108-0400