XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 66

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
4.16 I/O Limit Register
56
BIT
7:4
3:0
SCPS155C
This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream.
See Table 4−7 for a complete description of the register contents.
RESET STATE
BIT NUMBER
FIELD NAME
PCI register offset:
Register type:
Default value:
IOTYPE
IOLIMIT
ACCESS
7
0
RW
R
6
0
I/O limit. Defines the top address of the I/O address range that determines when to forward I/O
transactions from one interface to the other. These bits correspond to address bits [15:12] in the
I/O address. The lower 12 bits are assumed to be FFFh. The 16 bits corresponding to address bits
[31:16] of the I/O address are defined in the I/O limit upper 16 bits register (offset 32h, see
Section 4.25).
I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.
Table 4−7. I/O Limit Register Description
5
0
1Dh
Read-only, Read/Write
01h
4
0
3
0
2
0
1
0
DESCRIPTION
0
1
April 2007 Revised October 2008