XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 106

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

PCI Express Extended Configuration Space
5
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
96
SCPS155C
PCI Express Extended Configuration Space
The programming model of the PCI Express extended configuration space is compliant to the PCI Express
Base Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCI
Express extended configuration map uses the PCI Express advanced error reporting capability and PCI
Express virtual channel (VC) capability headers.
All bits marked with a
power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST, or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST,
GRST, or the internally-generated power-on reset.
Next capability offset / capability version
Next capability offset / capability version
VC resource status register (VC0)
VC resource status register (VC1)
Port VC status register
Table 5−1. PCI Express Extended Configuration Register Map
Secondary error capabilities and control register†
k
Secondary uncorrectable error severity register†
are sticky bits and are reset by a global reset (GRST) or the internally-generated
VC arbitration table (phase 23 − phase 16)
VC arbitration table (phase 15 − phase 8)
Advanced error capabilities and control†
VC arbitration table (phase 7 − phase 0)
Secondary uncorrectable error status†
Secondary uncorrectable error mask†
Uncorrectable error severity register†
VC resource capability register (VC0)
VC resource capability register (VC1)
Uncorrectable error status register†
Uncorrectable error mask register†
VC resource control register (VC0)
VC resource control register (VC1)
Correctable error status register†
Secondary header log register†
Secondary header log register†
Secondary header log register†
Secondary header log register†
Port VC capability register 1
Port VC capability register 2
Correctable error mask†
Header log register†
Header log register†
Header log register†
Header log register†
REGISTER NAME
Reserved
Reserved
PCI Express advanced error reporting capabilities ID
PCI express virtual channel extended capabilities ID
Port VC control register
Reserved
Reserved
April 2007 Revised October 2008
178h – 17Ch
OFFSET
10Ch
12Ch
13Ch
14Ch
15Ch
16Ch
100h
104h
108h
11Ch
120h
124h
128h
130h
134h
138h
140h
144h
148h
150h
154h
158h
160h
164h
168h
170h
174h
180h
184h
188h
110h
114h
118h