XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 45

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

3.5.3 PCI Express Extended VC With VC Arbitration
3.5.3.1
3.5.3.2
3.5.3.3
April 2007 Revised October 2008
Classic PCI configuration
register D4h
Classic PCI configuration
register 15Ch
When a second VC is enabled, the bridge has three arbitration options that determine which VC is granted
access to the upstream PCI Express link. These three arbitration modes include strict priority, hardware-fixed
round-robin, and 32-phase WRR. The default mode is strict priority. For all three arbitration modes, if the
second VC is disabled, then VC0 is always granted.
To map upstream transactions to the extended VC, the following registers must be programmed:
1. Bit 0 (ISOC_ENABLE) is asserted in the upstream isochrony control register at device control memory
2. At least one PCI isochronous window register set must be programmed. Please see Section 3.5.2 for a
3. The traffic class ID selected for the PCI isochronous window(s) must be assigned to the extended VC.
4. The extended VC must be enabled. This is accomplished by asserting bit 31 (VC_EN) and programming
Strict priority arbitration always grants VC1 traffic over VC0 traffic. If the traffic on VC1 uses 100% of the
upstream link bandwidth, then VC0 traffic is blocked. This mode is enabled when bit 25
(STRICT_PRIORITY_EN) in the general control register at offset D4h equals 1b (see Section 4.65).
For applications that require QoS or isochronous operation, this arbitration mode is recommended. In this
mode, all traffic on VC1 is assured access to the upstream link and VC0 traffic is best effort with a lower priority.
Hardware-fixed, round-robin arbitration alternates between VC0 and the second VC. Over an extended period
of time, if both VCs are heavily loaded with equal data payloads, each VC is granted approximately 50% of
the upstream link bandwidth. The PCI configuration registers described in Table 3−9 configure the
hardware-fixed, round-robin arbitration mode.
When the second upstream VC is enabled, the VC arbiter selects the next PCI Express upstream link
transaction based on entries within a VC arbitration table. There are actually two VC arbitration tables within
the bridge. The first table is accessed through the extended PCI Express configuration register space using
configuration read/write transactions. The second table is internal and is used by the VC arbiter to make
selection decisions. A configuration register load function exists to transfer the contents of the configuration
register table to the internal table.
The VC arbitration table uses a 4-bit field to identify the VC that is selected during each arbiter cycle. Bits 2:0
of this 4-bit field are loaded with the VC_ID assigned to each VC. For the arbiter to recognize a VC request,
the software must allocate only 1 phase to the same VC_ID.
The PCI configuration registers described in Table 3−10 configure the 32-phase, WRR arbitration mode.
PCI OFFSET
window register offset 04h (see Section 6.4).
description on how to program this advanced feature.
This is accomplished by asserting the corresponding bit in the TC_VC_MAP field in the VC resource
control register (VC1) at PCI Express extended register offset 170h (see Section 5.25).
bits 26:24 (VC_ID) in the VC resource control register (VC1) at PCI Express extended register offset 170h.
Strict Priority Arbitration Mode
Hardware-Fixed, Round-Robin Arbitration
32-Phase, WRR Arbitration Mode
Table 3−9. Hardware-Fixed, Round-Robin Arbiter Registers
General control
(see Section 4.65)
Port VC control
(see Section 5.19)
REGISTER NAME
Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed,
round-robin or 32-phase, WRR arbitration mode.
Bits 3:1 (VC_ARB_SELECT) equal to 000b enables hardware-fixed,
round-robin arbitration mode.
DESCRIPTION
Feature/Protocol Descriptions
SCPS155C
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