XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 125

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

5.25 VC Resource Control Register (VC1)
April 2007 Revised October 2008
30:27
26:24
23:20
19:17
15:8
BIT
7:0
31
16
The VC resource control register for VC1 allows software to control the second VC and associated port and
arbitration schemes supported by the bridge. See Table 5−21 for a complete description of the register
contents.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
FIELD NAME
LOAD_PORT
TC_VC_MAP
PORT_ARB
PCI Express extended register offset:
Register type:
Default value:
_SELECT
_TABLE
VC_EN
VC_ID
RSVD
RSVD
RSVD
ACCESS
Table 5−21. VC Resource Control Register (VC1) Description
31
15
0
0
RW
RW
RW
RW
RW
R
R
R
30
14
0
0
VC enable. This bit is used by software to enable this VC resource. Writing a 1b to this bit causes
the bridge to begin VC negotiation and set bit 1 (VC_PENDING) in the VC resource status register
for this VC (offset 176h, see Section 5.26). The default value for this bit is 0b.
Reserved. Returns 0h when read.
Virtual channel ID. This field allows software to assign a VC ID to this VC resource. Valid values
range from 001b to 111b, because the value 000b is hardware-fixed to VC0 within the device. The
default value for this field is 001b.
Reserved. Returns 0h when read.
Port arbitration select. This read/write field allows software to define the mechanism used for port
arbitration by the bridge on this VC. The value written to this field indicates the bit position within
bits 7:0 (PORT_ARB_CAP) in the VC resource capability register for this VC (offset 16Ch, see
Section 5.24) that corresponds to the selected arbitration scheme. Values that may be written to
this field include:
000 = Hardware-fixed round-robin (default)
100 = Time-based WRR with 128 phases
All other values are reserved for arbitrations schemes that are not supported by the bridge.
Load port arbitration table. When software writes a 1b to this bit, the bridge applies the values
written in the port arbitration table for this VC within the extended configuration space to the actual
port arbitration tables used by the device for arbitration on this VC. This bit always returns 0b when
read.
Reserved. Returns 00h when read.
TC/VC map. This field indicates all of the traffic classes that are mapped to this VC. A 1b in any bit
position indicates that the corresponding traffic class is enabled for this VC. A 0b indicates that the
corresponding traffic class is mapped to a different VC. The following table is used:
Bit 0 = Traffic class 0 (This bit is read only and returns a value of 0b)
Bit 1 = Traffic class 1
Bit 2 = Traffic class 2
Bit 3 = Traffic class 3
Bit 4 = Traffic class 4
Bit 5 = Traffic class 5
Bit 6 = Traffic class 6
Bit 7 = Traffic class 7
The default value of 00h indicates that none of the eight traffic classes are initially mapped to this
VC.
29
13
0
0
28
12
0
0
27
11
0
0
26
10
0
0
Read-only, Read/Write
0100 0000h
170h
25
0
9
0
24
1
8
0
DESCRIPTION
23
0
7
0
PCI Express Extended Configuration Space
22
0
6
0
21
0
5
0
20
0
4
0
19
0
3
0
SCPS155C
18
0
2
0
17
0
1
0
16
0
0
0
115