XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 41

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

3.4.5 MSI Messages Generated from the Serial IRQ Interface
April 2007 Revised October 2008
IRQ INTERRUPT
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
When properly configured, the bridge converts PCI bus serial IRQ interrupts into PCI Express message
signaled interrupts (MSI). classic PCI configuration register space is provided to enable this feature. The
following list identifies the involved configuration registers:
1. Command register at offset 04h, bit 2 (MASTER_ENB) is asserted (see Section 4.3).
2. MSI message control register at offset 62h, bits 0 (MSI_EN) and 6:4 (MM_EN) enable single and multiple
3. MSI message address register at offsets 64h and 68h specifies the message memory address. A nonzero
4. MSI message data register at offset 6Ch specifies the system interrupt message (see Section 4.41).
5. Serial IRQ mode control register at offset E0h specifies the serial IRQ bus format (see Section 4.72).
6. Serial IRQ edge control register at offset E2h selects either level or edge mode interrupts (see
7. Serial IRQ status register at offset E4h reports level mode interrupt status (see Section 4.74).
A PCI Express MSI is generated based on the settings in the serial IRQ edge control register. If the system
is configured for edge mode, then an MSI message is sent when the corresponding serial IRQ interface
sample phase transitions from low to high. If the system is configured for level mode, then an MSI message
is sent when the corresponding IRQ status bit in the serial IRQ status register changes from low to high.
The bridge has a dedicated SERIRQ terminal (T04) for all PCI bus devices that support serialized interrupts.
This SERIRQ interface is synchronous to the PCI bus clock input (CLK) frequency. The bridge always
generates a 17-phase serial IRQ stream. Internally, the bridge detects only 16 IRQ interrupts, IRQ0 frame
through IRQ15 frame. The IOCHCK frame is not monitored by the serial IRQ state machine and never
generates an IRQ interrupt or MSI message.
The multiple message enable (MM_EN) field determines the number of unique MSI messages that are sent
upstream on the PCI Express link. From 1 message to 16 messages, in powers of 2, are selectable. If fewer
than 16 messages are selected, then the mapping from IRQ interrupts to MSI messages is aliased. Table 3−4
illustrates the IRQ interrupt to MSI message mapping based on the number of enabling messages.
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
MSI messages, respectively (see Section 4.38).
address value in offset 68h initiates 64-bit addressing (see Section 4.40).
Section 4.73).
1 MESSAGE
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
ENABLED
Table 3−4. IRQ Interrupt to MSI Message Mapping
2 MESSAGES
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
ENABLED
4 MESSAGES
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
ENABLED
8 MESSAGES
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #4
MSI MSG #5
MSI MSG #6
MSI MSG #7
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #4
MSI MSG #5
MSI MSG #6
MSI MSG #7
ENABLED
Feature/Protocol Descriptions
SCPS155C
16 MESSAGES
MSI MSG #10
MSI MSG #12
MSI MSG #13
MSI MSG #14
MSI MSG #15
MSI MSG #11
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #4
MSI MSG #5
MSI MSG #6
MSI MSG #7
MSI MSG #8
MSI MSG #9
ENABLED
31