XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 62

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
4.4
52
10:9
BIT
2:0
15
14
13
12
11
8
7
6
5
4
3
SCPS155C
Status Register
The status register provides information about the PCI Express interface to the system. See Table 4−3 for a
complete description of the register contents.
RESET STATE
TABORT_REC
BIT NUMBER
TABORT_SIG
FIELD NAME
INT_STATUS
PCI_SPEED
PAR_ERR
SYS_ERR
PCI register offset:
Register type:
Default value:
DATAPAR
FBB_CAP
MABORT
CAPLIST
66MHZ
RSVD
RSVD
ACCESS
15
0
RCU
RCU
RCU
RCU
RCU
RCU
R
R
R
R
R
R
R
14
0
Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP. This
bit is set regardless of the state of bit 6 (PERR_ENB) in the command register (offset 04h, see
Section 4.3).
Signaled system error. This bit is set when the bridge sends an ERR_FATAL or ERR_NONFATAL
message and bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set.
Received master abort. This bit is set when the PCI Express interface of the bridge receives a
completion-with-unsupported-request status.
Received target abort. This bit is set when the PCI Express interface of the bridge receives a
completion-with-completer-abort status.
Signaled target abort. This bit is set when the PCI Express interface completes a request with
completer abort status.
DEVSEL timing. These bits are read-only 00b, because they do not apply to PCI Express.
Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command register (offset 04h,
see Section 4.3) is set and the bridge receives a completion with data marked as poisoned on the
PCI Express interface or poisons a write request received on the PCI Express interface.
Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express device
and is hardwired to 0b.
Reserved. Returns 0b when read.
66-MHz capable. This bit does not have a meaningful context for a PCI Express device and is
hardwired to 0b.
Capabilities list. This bit returns 1b when read, indicating that the bridge supports additional PCI
capabilities.
Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only 0b since
the bridge does not generate any interrupts internally.
Reserved. Returns 000b when read.
Table 4−3. Status Register Description
0 = No parity error detected
1 = Parity error detected
0 = No error signaled
1 = ERR_FATAL or ERR_NONFATAL signaled
0 = Unsupported request not received on the PCI Express interface
1 = Unsupported request received on the PCI Express interface
0 = Completer abort not received on the PCI Express interface
1 = Completer abort received on the PCI Express interface
0 = Completer abort not signaled on the PCI Express interface
1 = Completer abort signaled on the PCI Express interface
0 = No uncorrectable data error detected on the primary interface
1 = Uncorrectable data error detected on the primary interface
13
0
06h
Read-only, Read/Clear
0010h
12
0
11
0
10
0
9
0
8
0
DESCRIPTION
7
0
6
0
5
0
April 2007 Revised October 2008
4
1
3
0
2
0
1
0
0
0