MFRC52201HN1/TRAYB NXP [NXP Semiconductors], MFRC52201HN1/TRAYB Datasheet - Page 91

• Manufacturer Part Number: MFRC52201HN1/TRAYB
• Description: Contactless reader IC
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
25. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Selectable UART transfer speeds . . . . . . . . . .11
Table 11. UART framing . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 12. Read data byte order . . . . . . . . . . . . . . . . . . . .12
Table 13. Write data byte order . . . . . . . . . . . . . . . . . . . .13
Table 14. Address byte 0 register; address MOSI . . . . . .15
Table 15. Register and bit settings controlling the
Table 16. Register and bit settings controlling the
Table 17. CRC coprocessor parameters . . . . . . . . . . . . .27
Table 18. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .29
Table 19. Behavior of register bits and their designation .33
Table 20. MFRC522 register overview . . . . . . . . . . . . . .34
Table 21. Reserved register (address 00h); reset value:
Table 22. Reserved register bit descriptions . . . . . . . . . .36
Table 23. CommandReg register (address 01h); reset
Table 24. CommandReg register bit descriptions . . . . . .36
Table 25. ComIEnReg register (address 02h); reset value:
Table 26. ComIEnReg register bit descriptions . . . . . . . .37
Table 27. DivIEnReg register (address 03h); reset value:
Table 28. DivIEnReg register bit descriptions . . . . . . . . .37
Table 29. ComIrqReg register (address 04h); reset value:
Table 30. ComIrqReg register bit descriptions . . . . . . . .38
Table 31. DivIrqReg register (address 05h); reset value: x0h
Table 32. DivIrqReg register bit descriptions . . . . . . . . . .38
Table 33. ErrorReg register (address 06h); reset value: 00h
Table 34: ErrorReg register bit descriptions . . . . . . . . . .39
Table 35. Status1Reg register (address 07h); reset value:
Table 36. Status1Reg register bit descriptions . . . . . . . .40
MFRC522_33
Product data sheet
PUBLIC
Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Communication overview for
ISO/IEC 14443 A/MIFARE reader/writer . . . . . .7
Connection protocol for detecting different
interface types . . . . . . . . . . . . . . . . . . . . . . . . . .8
MOSI and MISO byte order . . . . . . . . . . . . . . . .9
MOSI and MISO byte order . . . . . . . . . . . . . . .10
Address byte 0 register; address MOSI . . . . . .10
BR_T0 and BR_T1 settings . . . . . . . . . . . . . . .11
signal on pin TX1 . . . . . . . . . . . . . . . . . . . . . . .23
signal on pin TX2 . . . . . . . . . . . . . . . . . . . . . . .24
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .36
value: 20h bit allocation . . . . . . . . . . . . . . . . . .36
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .36
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .37
14h bit allocation . . . . . . . . . . . . . . . . . . . . . . .37
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .38
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .39
21h bit allocation . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 3 — 26 October 2009
112133
Table 37. Status2Reg register (address 08h);
Table 38. Status2Reg register bit descriptions . . . . . . . . 41
Table 39. FIFODataReg register (address 09h);
Table 40. FIFODataReg register bit descriptions . . . . . . 42
Table 41. FIFOLevelReg register (address 0Ah);
Table 42. FIFOLevelReg register bit descriptions . . . . . . 42
Table 43. WaterLevelReg register (address 0Bh);
Table 44. WaterLevelReg register bit descriptions . . . . . 43
Table 45. ControlReg register (address 0Ch);
Table 46. ControlReg register bit descriptions . . . . . . . . 43
Table 47. BitFramingReg register (address 0Dh);
Table 48. BitFramingReg register bit descriptions . . . . . 44
Table 49. CollReg register (address 0Eh); reset value:
Table 50. CollReg register bit descriptions . . . . . . . . . . . 44
Table 51. Reserved register (address 0Fh); reset value:
Table 52. Reserved register bit descriptions . . . . . . . . . . 45
Table 53. Reserved register (address 10h); reset value:
Table 54. Reserved register bit descriptions . . . . . . . . . . 45
Table 55. ModeReg register (address 11h); reset value:
Table 56. ModeReg register bit descriptions . . . . . . . . . . 46
Table 57. TxModeReg register (address 12h); reset value:
Table 58. TxModeReg register bit descriptions . . . . . . . . 47
Table 59. RxModeReg register (address 13h); reset value:
Table 60. RxModeReg register bit descriptions . . . . . . . 47
Table 61. TxControlReg register (address 14h);
Table 62. TxControlReg register bit descriptions . . . . . . 48
Table 63. TxASKReg register (address 15h); reset value:
Table 64. TxASKReg register bit descriptions . . . . . . . . 49
Table 65. TxSelReg register (address 16h); reset value:
Table 66. TxSelReg register bit descriptions . . . . . . . . . 49
Table 67. RxSelReg register (address 17h); reset value:
Table 68. RxSelReg register bit descriptions . . . . . . . . . 50
reset value: 00h bit allocation . . . . . . . . . . . . . 41
reset value: xxh bit allocation . . . . . . . . . . . . . 42
reset value: 00h bit allocation . . . . . . . . . . . . . 42
reset value: 08h bit allocation . . . . . . . . . . . . . 42
reset value: 10h bit allocation . . . . . . . . . . . . . 43
reset value: 00h bit allocation . . . . . . . . . . . . . 44
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 44
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 45
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 45
3Fh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 46
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 46
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 47
reset value: 80h bit allocation . . . . . . . . . . . . . 48
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 49
10h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 49
84h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 50
Contactless reader IC
MFRC522
© NXP B.V. 2009. All rights reserved.
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