MFRC52201HN1/TRAYB NXP [NXP Semiconductors], MFRC52201HN1/TRAYB Datasheet - Page 32

• Manufacturer Part Number: MFRC52201HN1/TRAYB
• Description: Contactless reader IC
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
MFRC522_33
Product data sheet
PUBLIC
8.8.1 Reset timing requirements
8.8.2 Oscillator start-up time
8.8 Reset and oscillator start-up time
The clock applied to the MFRC522 provides a time basis for the synchronous system’s
encoder and decoder. The stability of the clock frequency, therefore, is an important factor
for correct operation. To obtain optimum performance, clock jitter must be reduced as
much as possible. This is best achieved using the internal oscillator buffer with the
recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, special care must be taken with the clock duty cycle and clock jitter and the clock
quality must be verified.
The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the
digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a
reset, the signal must be LOW for at least 100 ns.
If the MFRC522 has been set to a Power-down mode or is powered by a V
start-up time for the MFRC522 depends on the oscillator used and is shown in
The time (t
start-up time is defined by the crystal.
The time (t
before the MFRC522 can be addressed.
The delay time is calculated by:
The time (t
t
d
Fig 23. Oscillator start-up time
=
device activation
------------- -
27 s
1024
clock stable
clock ready
oscillator
startup
d
osc
) is the internal delay time of the MFRC522 when the clock signal is stable
=
) is the sum of t
37.74 s
) is the start-up time of the crystal oscillator circuit. The crystal oscillator
Rev. 3 — 26 October 2009
d
112133
and t
startup
.
t
startup
t
osc
Contactless reader IC
MFRC522
© NXP B.V. 2009. All rights reserved.
t
d
DDX
001aak596
supply, the
Figure
32 of 96
t
23.
(6)