MFRC52201HN1/TRAYB NXP [NXP Semiconductors], MFRC52201HN1/TRAYB Datasheet - Page 28

• Manufacturer Part Number: MFRC52201HN1/TRAYB
• Description: Contactless reader IC
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
MFRC522_33
Product data sheet
PUBLIC
8.4.1 Interrupt sources overview
8.4 Interrupt request system
The MFRC522 can generate an interrupt signal when:
If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less
are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to
Equation
If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored
in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to
The MFRC522 indicates certain events by setting the Status1Reg register’s IRq bit and, if
activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its
interrupt handling capabilities. This allows the implementation of efficient host software.
Table 18
its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by
the timer unit which is set when the timer decrements from 1 to 0.
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by
CRCReady bit = 1.
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and
the Command[3:0] value in the CommandReg register changes to idle (see
page
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
HiAlert
LoAlert
•
•
•
•
FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit
FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit can
only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.
ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s LoAlert bit changes to logic 1.
ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s HiAlert bit changes to logic 1.
67).
=
shows the available interrupt bits, the corresponding source and the condition for
=
3:
FIFOLength WaterLevel
64 FIFOLength
–
Rev. 3 — 26 October 2009
112133
WaterLevel
Contactless reader IC
MFRC522
© NXP B.V. 2009. All rights reserved.
Table 149 on
Equation
28 of 96
(3)
(4)
4: