MFRC52201HN1/TRAYB NXP [NXP Semiconductors], MFRC52201HN1/TRAYB Datasheet - Page 38

• Manufacturer Part Number: MFRC52201HN1/TRAYB
• Description: Contactless reader IC
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
MFRC522_33
Product data sheet
PUBLIC
9.3.1.6 DivIrqReg register
Table 30.
All bits in the ComIrqReg register are cleared by software.
Interrupt request bits.
Table 31.
Table 32.
All bits in the DivIrqReg register are cleared by software.
Bit Symbol
7
6
5
4
3
2
1
0
Bit
7
6 to 5 reserved
4
3
2
1 to 0 reserved
Bit
Symbol
Access
Set1
TxIRq
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq 1
ErrIRq
TimerIRq
Symbol
Set2
MfinActIRq 1
reserved
CRCIRq
ComIrqReg register bit descriptions
DivIrqReg register (address 05h); reset value: x0h bit allocation
DivIrqReg register bit descriptions
Set2
W
7
Value Description
1
0
1
1
1
1
1
1
Value Description
1
0
-
-
1
-
6
Rev. 3 — 26 October 2009
reserved
indicates that the marked bits in the ComIrqReg register are set
indicates that the marked bits in the ComIrqReg register are cleared
set immediately after the last bit of the transmitted data was sent out
receiver has detected the end of a valid data stream
if the RxModeReg register’s RxNoErr bit is set to logic 1, the RxIRq bit is
only set to logic 1 when data bytes are available in the FIFO
If a command terminates, for example, when the CommandReg changes
its value from any command to the Idle command (see
page
if an unknown command is started, the CommandReg register
Command[3:0] value changes to the idle state and the IdleIRq bit is set
The microcontroller starting the Idle command does not set the IdleIRq
bit
the Status1Reg register’s HiAlert bit is set
in opposition to the HiAlert bit, the HiAlertIRq bit stores this event and
can only be reset as indicated by the Set1 bit in this register
Status1Reg register’s LoAlert bit is set
in opposition to the LoAlert bit, the LoAlertIRq bit stores this event and
can only be reset as indicated by the Set1 bit in this register
any error bit in the ErrorReg register is set
the timer decrements the timer value in register TCounterValReg to zero
indicates that the marked bits in the DivIrqReg register are set
indicates that the marked bits in the DivIrqReg register are cleared
reserved for future use
MFIN is active
this interrupt is set when either a rising or falling signal edge is
detected
reserved for future use
the CalcCRC command is active and all data is processed
reserved for future use
-
67)
112133
5
MfinActIRq
D
4
reserved
3
-
CRCIRq
D
2
Contactless reader IC
MFRC522
© NXP B.V. 2009. All rights reserved.
Table 149 on
1
reserved
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