FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 96

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FDC37C669_07

Manufacturer Part Number
FDC37C669_07
Description
PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
Manufacturer
SMSC [SMSC Corporation]
Datasheet
EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of
which are listed below. The individual features
are explained in greater detail in the remainder
of this section.
Vocabulary
The following terms are used in this document:
assert When
forward Host to Peripheral communication.
reverse Peripheral to Host communication.
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
data
ecpAFifo Addr/RL
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
High performance half-duplex forward and
reverse channel
Interlocked handshake, for fast reliable
transfer
Optional single byte RLE compression for
improved throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
transitions to a "true" state, when a
signal deasserts it transitions to a
"false" state.
compress
nBusy
PD7
D7
E
0
0
a
intrValue
MODE
nAck
PD6
signal
D6
0
0
Direction
PError
PD5
asserts
D5
0
0
Parallel Port Data FIFO
ECP Data FIFO
nErrIntrEn
ackIntEn SelectIn
Select
Test FIFO
it
PD4
Address or RLE field
D4
1
0
96
PWord A port word; equal in size to the
1
0
These terms may be considered synonymous:
Reference Document:
IEEE 1284 Extended Capabilities Port Protocol
and ISA Interface Standard, Rev 1.09, Jan 7,
1993.
Microsoft.
The bit map of the Extended Parallel Port
registers is:
dmaEn
nFault
PD3
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
D3
0
0
width of the ISA interface.
implementation, PWord is always 8
bits.
A high level.
A low level.
This document is available from
serviceIntr
PD2
nInit
D2
0
0
0
autofd strobe
PD1
D1
full
0
0
0
empty
PD0
D0
0
0
0
For this
Note
2
1
1
2
2
2

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