FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 122

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FDC37C669_07

Manufacturer Part Number
FDC37C669_07
Description
PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
Manufacturer
SMSC [SMSC Corporation]
Datasheet
CR01
This register can only be accessed in the
Configuration
CR02
This register can only be accessed in the
Configuration Mode and after the CSR has been
Note_PWRDN:
BIT NO.
BIT NO.
0,1
5,6
0:2
4:6
2
3
4
7
3
7
Mode
Reserved
Parallel Port
Power (see note
_PWRDN)
Parallel Port
Mode
Reserved
Reserved
Lock CRx
Reserved
UART1 Power
down (see note
_PWRDN)
Reserved
UART2 Power
down
Power Down bits disable the respective logical device and associated pins, however
the power down bit does not disable the selected address range registers for the
logical device.
address must be set below 100h. Therefore devices which are powered down, but
still reside at a valid I/O base address will participate in Plug-and-Play range
checking.
BIT NAME
BIT NAME
and after the CSR has
To disable the host address registers the logical device's base
Read Only. A read returns a 0.
A high level on this bit, supplies power to the Parallel Port
(Default). A low level on this bit puts the Parallel Port in low
power mode.
Parallel Port Mode. A high level on this bit, sets the Parallel Port
for Printer Mode (Default). A low level on this bit enables the
Extended Parallel port modes. Refer to Bits 0 and 1 of CR4
Read Only. A read returns a 1.
Read Only. A read returns a 0.
A high level on this bit enables the reading and writing of CR00-
CR18 (Default). A low level on this bit disables the reading and
writing of CR0-CRF. Once set to 0, this bit can only be set to 1
by a hard reset or power-up reset.
Read Only. A read returns a 0.
A high level on this bit, allows normal operation of the Primary
Serial Port (Default). A low level on this bit places the Primary
Serial Port into Power Down Mode.
Read Only. A read returns a 0.
A high level on this bit, allows normal operation of the Secondary
Serial Port (Default). A low level on this bit places the Secondary
Serial Port into Power Down Mode.
Table 48 - CR01
Table 49 - CR02
122
been initialized to 01H. The default value of this
register after power up is 9CH.
initialized to 02H.
register after power up is 88H.
DESCRIPTION
DESCRIPTION
The default value of this

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