FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 127

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

CR08
This register can only be accessed in the
Configuration Mode and after the CSR has been
initialized to 08H.
register after power up is 00H. This is the lower
4 bits (ADRA7:4) for the ADRx address decode.
The non-programmable
default to 0000b.
CR0A
This register can only be accessed in the
Configuration Mode and after the CSR has been
initialized to 0AH.
CR0B
This register can only be ac1cessed in the
Configuration Mode and after the CSR has
been initialized to 0BH. The default value of
DRT1
D7
D7
RESERVED - READ ONLY 0 HEX
Upper Address Decode requirements : nCS='0' is required to qualify the ADRx output.
FDD3
DRT0
D6
D6
The default value of this
The default value of this
address
DRT1
D5
D5
D7
0
0
1
1
FDD2
bits
D6
0
1
0
1
DRT0
Table 54 - CR0A
Table 55 - CR0B
D4
D4
3:0
ADRx Configuration
127
16 byte block decode
8 Byte block decode
ADRx disabled
A[3:0]=XXXXb
1 Byte decode
A[3:0]=0XXXb
A[3:0]=0000b
CR09
This register can only be accessed in the
Configuration Mode and after the CSR has been
initialized to 09H.
register after power up is 00H. This is the upper
3 bits (ADRA10:8) (D2 - MSB, D0 - LSB) for the
ADRx address decode. ADRx Config (bits 7:6)
define the configuration of the ADRx decoder as
follows:
register after power up is 00H. This byte defines
the FIFO threshold for the ECP mode parallel
port.
this register after power up is 00H. This register
indicates the data rate table used for each drive.
THR3
Refer to CR1F for Drive Type register.
DRT1
D3
D3
ECP F I F O T H R E S H O L D
FDD1
THR2
DRT0
D2
D2
The default value of this
THR1
DRT1
D1
D1
FDD0
THR0
DRT0
D0
D0