FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 73

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

The FDC37C669 incorporates two full function
UARTs.
NS16450, the 16450 ACE registers and the
NS16550A.
parallel conversion on received characters and
parallel-to-serial
characters. The data rates are independently
programmable from 115.2K baud down to 50
baud. The character options are programmable
for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky
or no parity; and prioritized interrupts. The
UARTs each contain a programmable baud rate
generator that is capable of dividing the input
clock or crystal by a number from 1 to 65535.
The UARTs are also capable of supporting the
MIDI data rate. Refer to the FDC37C669
Configuration Registers
They
The UARTs
DLAB*
0
0
0
X
X
X
X
X
X
X
1
1
conversion
are
compatible
*NOTE: DLAB is Bit 7 of the Line Control Register
A2
0
0
0
0
0
0
1
1
1
1
0
0
for information on
perform
Table 31 - Addressing the Serial Port
on
A1
0
0
0
1
1
1
0
0
1
1
0
0
SERIAL PORT (UART)
with
serial-to-
transmit
A0
0
0
1
0
0
1
0
1
0
1
0
1
the
73
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write)
disabling, power down and changing the base
address of the UARTs.
UART is enabled by programming OUT2 of that
UART to a logic "1". OUT2 being a logic "0"
disables that UART's interrupt.
REGISTER DESCRIPTION
Addressing of the accessible registers of the
Serial Port is shown below.
addresses of the serial ports are defined by the
configuration
section). The Serial Port registers are located at
sequentially increasing addresses above these
base addresses. The FDC37C669 contains two
serial ports, each of which contain a register set
as described below.
REGISTER NAME
registers
The interrupt from a
(see
Configuration
The base