FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 130

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

CR10
This register can only be accessed in the
Configuration Mode and after the CSR has been
CR11
This register can only be accessed in the
Configuration Mode and after the CSR has
BIT NO.
BIT NO.
0 - 2
2 - 7
3
4
5
6
7
0
1
Infra Red Test This bit enables the IR test mode. When this bit is set to a 1 the
IR Loop Back
ACE_STOP
BIT NAME
BIT NAME
Test 10ms
PLL Clock
Reserved
Reserved
Pll Gain
Pll Stop
Control
Reserved - READ ONLY. A read returns a 0.
This bit controls the gain of the frequency multiplying phase lock
loops. When a 0 (default) the gain is set to a value expected for 5
volt operation. When set to a 1 the gain is doubled to a value for
possible 3 volt operation.
A 1 in this bit position stops the frequency multiplying phase lock
loops. A 0 (default) allows normal operation.
This bit when set to a 1 will inhibit the 24MHz clock to the divide by
12/13 that generates the UART clocks, and reset those dividers.
When at a 0 (default) these dividers and clocks are enabled.
This bit enables the PLL clock generator to run with either a
14.318MHz or 24MHz input clock. A 0 enables the 14.318MHz clock
(default), a 1 enables the 24MHz clock.
serial data seen by UART RX and TX ports is output on SOUT. A 0
gives normal operation (default).
When a 1 the IROUT is looped back internally to the IRIN input.
When a 0 (default) normal operation.
This bit when a 1 tests the 10ms timeout of the FDC autopower down
mode. A 0 (default) allows normal operation.
Reserved - READ ONLY. A read returns a 0.
Table 58 - CR10
Table 59 - CR11
130
initialized to 10H.
register after power up is 00H.
been initialized to 11H. The default value of this
register after power up is 00H.
DESCRIPTION
DESCRIPTION
The default value of this