FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 128

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

CR0C
This register can only be accessed in the
Configuration Mode and after the CSR has been
initialized to 0CH.
CR0D
This register can only be accessed in the
Configuration Mode and after the CSR has been
initialized to 0DH.
This is the Device ID. The default value of this
register after power up is 03H.
BIT NO.
3, 4, 5
0
1
2
6
7
This register is read only.
The default value of this
UART 2 Duplex This bit is used to define the FULL/HALF
UART 2 MODE UART 2 Mode
UART 1 Speed This bit enables the high speed mode of UART
UART 2 XMIT
UART 2 RCV
UART Speed
BIT NAME
Polarity
Polarity
Table 56 - CR0C
1 = RX input inverted.
0 = RX input non - inverted (default).
1 = TX output inverted.
0 = TX output non - inverted (default).
DUPLEX operation of UART 2.
1 = Half duplex
0 = Full duplex (default)
5 4 3
0 0 0Standard (default)
0 0 1IrDA (HPSIR)
0 1 0Amplitude Shift Keyed IR @ 500Khz
0 1 1Reserved
1 x xReserved
1 = High speed enabled
0 = Standard (default)
This bit enables the high speed mode of UART
1 = High speed enabled
0 = Standard (default)
128
register after power up is 00H.
controls the operating mode of the UART. This
register is reset to the default state by a POR or
a hardware reset.
CR0E
This register can only be accessed in the
Configuration Mode and after the CSR has been
initialized to 0EH. This register is read only. The
default value of this register after power up is
02H. This is used to identify the chip revision
level.
DESCRIPTION
This register