FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 133

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

CR21
This register can only be accessed in the
Configuration Mode and after the CSR has been
initialized to 21H. The default value of this
register after
register is used to select the base address of the
IDE Interface Control Registers (0-7).
CR22
This register can only be accessed in the
Configuration Mode and after the CSR has been
initialized to 22H.
register after power up is 3DH. This register
is used to select the base address of the
IDE Interface Alternate Status Register. This
can be set to 48 locations, on 16 byte
CR23
This register can only be accessed in the
Configuration Mode and after the CSR has been
initialized to 23H.
register after power up is 00H. This register is
used to select the base address of the parallel
port. If EPP is not enabled, the parallel port can
be set to 192 locations, on 4 byte boundaries
from 100H-3FCH.
ADR9
ADR9
ADR9
DB7
DB7
DB7
ADR8
ADR8
ADR8
DB6
DB6
DB6
power
The default value of this
The default value of this
If EPP is enabled, the
EPP Enabled
up
ADR7
ADR7
ADR7
Yes
DB5
DB5
DB5
No
is 3CH.
ADR6
ADR6
ADR6
A[1:0] = XXb
A[2:0] = XXXb
DB4
DB4
DB4
This
This
Addressing (low bits) Decode
133
can be set to 48 locations, on 16 byte
boundaries from 100H-3F0H.
decode, set ADR9 and ADR8 to zero.
Upper Address Decode requirements : nCS='0'
and A10='0' are required to access the IDE
registers. A[3:0] are decoded as 0XXXb.
boundaries+6 from 106H-3F6H. To disable this
decode, set ADR9 and ADR8 to zero.
Upper Address Decode requirements: nCS='0'
and A10='0' are required to access the IDE
Alternate Status register. A[3:0] must be 0110b.
parallel port can be set to 96 locations, on 8
byte boundaries from 100H-3F8H.
the parallel port, set ADR9 and ADR8 to zero.
Upper Address Decode requirements: nCS='0'
and A10='0' are required to access the Parallel
Port when in Compatible, Bi-directional, or EPP
modes (A10 is active when in ECP mode).
ADR5
ADR5
ADR5
DB3
DB3
DB3
ADR4
ADR4
ADR4
DB2
DB2
DB2
ADR3
DB1
DB1
DB1
0
0
To disable this
To disable
ADR2
DB0
DB0
DB0
0
1