PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 95

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

9.0
Depending on the device selected, there are up to five
general purpose I/O ports available on PIC18FXX8
devices. Some pins of the I/O ports are multiplexed
with an alternate function from the peripheral features
on the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
Each port has three registers for its operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
• LAT register (output latch).
The
read-modify-write operations on the value that the I/O
pins are driving.
9.1
PORTA is a 7-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= ‘1’) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISA bit (= ‘0’)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
On a Power-on Reset, these pins are configured as
inputs and read as '0'.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
Read-modify-write operations on the LATA register,
reads and writes the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The
RA4/T0CKI pin is a Schmitt Trigger input and an open
drain output. All other RA port pins have TTL input
levels and full CMOS output drivers.
The other PORTA pins are multiplexed with analog
inputs and the analog V
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1). On a Power-on Reset, these pins are
configured as analog inputs and read as '0'.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set, when using them as analog inputs.
EXAMPLE 9-1:
 2002 Microchip Technology Inc.
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
device)
data
I/O PORTS
PORTA, TRISA and LATA
Registers
PORTA ; Initialize PORTA by
LATA
07h
ADCON1 ; for digital inputs
0xCF
TRISA ; Set RA3:RA0 as inputs,
latch
; clearing output data latches
; Alternate method to clear
; output data latches
; C onfigure A/D
; Value used to initialize
; data direction
; RA5:RA4 as outputs
(LAT
INITIALIZING PORTA
REF
register)
+ and V
REF
is
- inputs. The
useful
Preliminary
for
FIGURE 9-1:
FIGURE 9-2:
Note 1: I/O pin has diode protection to V
RD LATA
Data Bus
RD TRISA
RD PORTA
WR LATA or
WR PORTA
WR TRISA
Analog
Input Mode
RD LATA
Data Bus
WR LATA
WR PORTA
WR TRISA
RD TRISA
RD PORTA
Note 1: I/O pins have diode protection to V
To A/D Converter and LVD Modules
TMR0 Clock Input
SS Input (RA5 only)
or
TRIS Latch
Data Latch
D
Data Latch
TRIS Latch
D
D
CK
CK
D
CK
CK
Q
Q
Q
Q
RA3:RA0 AND RA5 PINS
BLOCK DIAGRAM
Q
RA4/T0CKI PIN BLOCK
DIAGRAM
Q
Q
Q
PIC18FXX8
Q
Q
TTL
Input
Buffer
EN
SS
D
V
EN
N
DS41159B-page 93
only.
SS
D
DD
V
V
P
N
SS
DD
and V
SS
TTL
Input
Buffer
I/O pin
I/O pin
.
Schmitt
Trigger
Input
Buffer
(1)
(1)