PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 28

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX8
3.1
A Power-on Reset pulse is generated on-chip when a
V
cuitry, connect the MCLR pin directly (or through a
resistor) to V
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for V
parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met. Brown-out Reset may be used to meet
the voltage start-up condition.
3.2
PIC18FXX8 devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can
result in both resets and current draws outside of
device specification during the RESET event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to V
network, as shown in Figure 3-2, is suggested.
FIGURE 3-2:
DS41159B-page 26
DD
rise is detected. To take advantage of the POR cir-
V
DD
Power-on Reset (POR)
MCLR
R1
1 k Ω (or greater)
C1
0.1 µ F
(not critical)
DD
. This eliminates external RC compo-
RECOMMENDED MCLR
CIRCUIT
DD
DD
. The use of an RC
is specified (refer to
MCLR
PIC18FXX8
Preliminary
3.3
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT’s time delay allows V
acceptable level. A configuration bit (PWRTEN in
CONFIG2L register) is provided to enable/disable the
PWRT.
The power-up time delay will vary from chip to chip due
to V
parameter #33 for details.
3.4
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This additional
delay ensures that the crystal oscillator or resonator
has started and stabilized.
The OST time-out is invoked only for XT, LP, HS and
HS4 modes and only on Power-on Reset or wake-up
from SLEEP.
3.5
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(T
start-up time-out (OST).
3.6
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set), the Brown-out Reset
circuitry. If V
than parameter #35, the brown-out situation resets the
chip. A RESET may not occur if V
eter D005 for less than parameter #35. The chip will
remain in Brown-out Reset until V
The Power-up Timer will then be invoked and will keep
the chip in RESET an additional time delay (parameter
#33). If V
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
V
execute the additional time delay.
DD
PLL
DD
) is typically 2 ms and follows the oscillator
rises above BV
, temperature and process variation. See DC
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
DD
DD
drops below BV
falls below parameter D005 for greater
DD
 2002 Microchip Technology Inc.
, the Power-up Timer will
DD
DD
DD
while the Power-up
rises above BV
falls below param-
DD
to rise to an
DD
.