PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 90

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX8
8.4
The Interrupt Priority (IPR) registers contain the individ-
ual priority bits for the peripheral interrupts. Due to the
number of peripheral interrupt sources, there are three
Peripheral Interrupt Priority registers (IPR1, IPR2 and
IPR3). The operation of the priority bits requires that
the Interrupt Priority Enable bit (IPEN) be set.
REGISTER 8-10:
DS41159B-page 88
IPR Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (IPR1)
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1 = High priority
0 = Low priority
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
RCIP: USART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
TXIP: USART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
CCP1IP: CCP1 Interrupt Priority bit
1 =High priority
0 =Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
Legend:
R = Readable bit
- n = Value at POR
PSPIP
R/W-1
(1)
is unimplemented and reads as ’0’.
R/W-1
ADIP
R/W-1
RCIP
Preliminary
W = Writable bit
’1’ = Bit is set
R/W-1
TXIP
SSPIP
R/W-1
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
(1)
CCP1IP
R/W-1
 2002 Microchip Technology Inc.
x = Bit is unknown
TMR2IP
R/W-1
TMR1IP
R/W-1
bit 0