PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 311

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
2002 Microchip Technology Inc.
After Interrupt
operation
Decode
No
PC = TOS
Q1
operation
operation
Return from Subroutine
[ label ]
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’= 1, the contents of the
shadow registers WS, STATUSS
and BSRS are loaded into their cor-
responding registers, W, STATUS
and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
1
2
RETURN
0000
No
No
Q2
[0,1]
W,
PC,
RETURN [s]
0000
BSR,
operation
Process
Data
No
STATUS,
Q3
0001
pop PC from
operation
stack
No
Q4
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register ’f’
Rotate Left f through Carry
[ label ]
0
d
a
(f<n>)
(f<7>)
(C)
C, N, Z
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0, the result
is placed in W. If 'd' is 1, the result
is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
RLCF
Read
Q2
0011
1110 0110
0
1110 0110
1100 1100
1
f
[0,1]
[0,1]
PIC18FXX8
C
dest<0>
255
dest<n+1>,
C,
RLCF
01da
Process
Data
Q3
REG, W
register f
DS41159B-page 309
f [,d [,a]]
ffff
destination
Write to
Q4
ffff