PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 163
PIC18F258
Manufacturer Part Number
PIC18F258
Description
High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F258.pdf
(384 pages)
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17.4.4.5
If a user clears the CKP bit, the SCL output is forced to
‘0’. Setting the CKP bit will not assert the SCL output
low until the SCL output is already sampled low. If the
user attempts to drive SCL low, the CKP bit will not
FIGURE 17-12:
2002 Microchip Technology Inc.
WR
SSPCON
SDA
SCL
CKP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Clock Synchronization and
the CKP bit
CLOCK SYNCHRONIZATION TIMING
DX
Master device
asserts clock
Preliminary
assert the SCL line until an external I
has already asserted the SCL line. The SCL output will
remain low until the CKP bit is set, and all other devices
on the I
that a write to the CKP bit will not violate the minimum
high time requirement for SCL (see Figure 17-12).
Master device
de-asserts clock
2
C bus have de-asserted SCL. This ensures
PIC18FXX8
DS41159B-page 161
2
C master device
DX-1
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