PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 143

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

17.0
17.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode
17.2
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I
Additional details are provided under the individual
sections.
 2002 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
2
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
Control Registers
2
C)
2
C mode.
Preliminary
17.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four modes
of SPI are supported. To accomplish communication,
typically three pins are used:
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) - RF7/SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
RC4/SDI/SDA
RC3/SCK/
RC5/SDO
RF7/SS
SCL
SPI Mode
Read
SS Control
Select
SMP:CKE
Edge
Enable
bit0
MSSP BLOCK DIAGRAM
(SPI MODE)
Select
Edge
PIC18FXX8
TRIS bit
Data to TX/RX in SSPSR
SSPBUF reg
2
SSPM3:SSPM0
SSPSR reg
Clock Select
4
2
DS41159B-page 141
(
Prescaler
TMR2 Output
4, 16, 64
Write
Clock
Shift
Data Bus
Internal
2
T
OSC
)