PIC17C752-08/CL MICROCHIP [Microchip Technology], PIC17C752-08/CL Datasheet - Page 45

• Manufacturer Part Number: PIC17C752-08/CL
• Description: High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 7-5:
Addr
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Fh
20h
FFh
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All unbanked SFRs
1998 Microchip Technology Inc.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh are
3: RAM bank 3 is not implemented on the PIC17C752 and the PIC17C762. Reading any unimplemented regis-
4: Bank 8 is only implemented on the PIC17C76X devices.
Unbanked
Unbanked
TBLPTRH
Bank 0
TBLPTRL
RCREG1
SPBRG1
CPUSTA
TXREG1
PCLATH
ALUSTA
RCSTA1
Purpose
Purpose
TXSTA1
PRODH
INTSTA
TMR0H
General
General
TMR0L
Bank 0
PORTA
PORTB
PRODL
ignore the Bank Select Register (BSR) bits.
banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select Register
(BSR) bits.
ter reads ‘0’s.
T0STA
WREG
INDF0
INDF1
DDRB
FSR0
FSR1
RAM
RAM
BSR
PCL
(2)
PIC17C7XX REGISTER FILE MAP
Bank 1
Bank 1
Purpose
PORTC
PORTD
General
PORTE
DDRC
DDRD
DDRE
PIR1
RAM
PIE1
(1)
(2)
PR3H/CA1H
PR3L/CA1L
Bank 2
Bank 2
Purpose
TMR3H
General
TMR3L
TMR1
TMR2
RAM
PR1
PR2
(2, 3)
(1)
Bank 3
Bank 3
PW1DCH
PW2DCH
PW1DCL
PW2DCL
Purpose
General
TCON1
TCON2
CA2H
CA2L
RAM
(2, 3)
(1)
Bank 4
RCREG2
TXREG2
SPBRG2
RCSTA2
TXSTA2
PIR2
PIE2
—
(1)
Bank 5
ADCON0
ADCON1
ADRESH
ADRESL
PORTG
PORTF
DDRG
DDRF
(1)
SSPCON1
SSPCON2
Bank 6
SSPSTAT
SSPADD
SSPBUF
—
—
—
PIC17C7XX
(1)
Bank 7
PW3DCH
PW3DCL
TCON3
CA3H
CA4H
CA3L
CA4L
—
DS30289A-page 45
(1)
Bank 8
PORTH
PORTJ
DDRH
DDRJ
—
—
—
—
(1, 4)