PIC17C752-08/CL MICROCHIP [Microchip Technology], PIC17C752-08/CL Datasheet - Page 191

• Manufacturer Part Number: PIC17C752-08/CL
• Description: High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

17.3
The Watchdog Timer’s function is to recover from
software malfunction. The WDT uses an internal free
running on-chip RC oscillator for its clock source. This
does not require any external components. This RC
oscillator is separate from the RC oscillator of the
OSC1/CLKIN pin. That means that the WDT will run,
even
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation, a WDT time-out generates a device RESET.
The
programming the configuration bits WDTPS1:WDTPS0
as '00'
Under normal operation, the WDT must be cleared on
a regular interval. This time must be less than the min-
imum WDT overflow time. Not clearing the WDT in this
time frame will cause the WDT to overflow and reset the
device.
17.3.1
The WDT has a nominal time-out period of 12 ms, (with
postscaler = 1). The time-out periods vary with temper-
ature, V
DC specs). If longer time-out periods are desired, con-
figuration bits should be used to enable the WDT with
a greater prescale. Thus, typical time-out periods up to
3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and its postscale setting and prevent it from timing out
thus generating a device RESET condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
FIGURE 17-2: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 17-2:
Address
06h, Unbanked CPUSTA
Legend:
Note 1:
Note 1: This oscillator is separate from the external
1998 Microchip Technology Inc.
—
WDT
(Section
if
DD
Watchdog Timer (WDT)
WDT PERIOD
- = unimplemented read as '0', q - value depends on condition, shaded cells are not used by the WDT.
This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
RC oscillator on the OSC1 pin.
and process variations from part to part (see
the
On-chip RC
Oscillator
can
Name
Config
17.1).
clock
REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
be
(1)
on
See
permanently
Bit 7
—
Figure 17-1
WDT Enable
the
WDT
Bit 6
OSC1/CLKIN
—
for location of WDTPSx bits in Configuration Word.
disabled
STKAV
Bit 5
GLINTD
and
Bit 4
by
Bit 3
TO
17.3.2
The WDT and postscaler are cleared when:
• The device is in the reset state
• A SLEEP instruction is executed
• A CLRWDT instruction is executed
• Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the reset state.
17.3.3
It should also be taken in account that under worst case
conditions (V
WDT postscaler) it may take several seconds before a
WDT time-out occurs.
The WDT and postscaler become the Power-up Timer
whenever the PWRT is invoked.
17.3.4
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
flow time is 65536 T
is cleared (device is not reset). The CLRWDT instruction
can be used to set the TO bit. This allows the WDT to
be a simple overflow timer. The simple timer does not
increment when in sleep.
Bit 2
PD
CLEARING THE WDT AND POSTSCALER
WDT PROGRAMMING CONSIDERATIONS
WDT AS NORMAL TIMER
4 - to - 1 MUX
WDT Overflow
Postscaler
DD
Bit 1
POR
= Min., Temperature = Max., max.
OSC
cycles. On overflow, the TO bit
Bit 0
BOR
PIC17C7XX
WDTPS1:WDTPS0
--11 11qq
Value on
(Note 1)
POR,
BOR
DS30289A-page 191
MCLR, WDT
--11 qquu
(Note 1)