PIC17C752-08/CL MICROCHIP [Microchip Technology], PIC17C752-08/CL Datasheet - Page 148

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PIC17C752-08/CL

Manufacturer Part Number
PIC17C752-08/CL
Description
High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
PIC17C7XX
15.2.3
While in sleep mode, the I
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep (if the SSP interrupt is enabled).
TABLE 15-3:
DS30289A-page 148
Address
07h, Unbanked INTSTA
10h, Bank 4
11h, Bank 4
10h. Bank 6
14h, Bank 6
11h, Bank 6
12h, Bank 6
13h, Bank 6
Legend:
SLEEP OPERATION
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I
Name
PIR2
PIE2
SSPADD
SSPBUF
SSPCON1
SSPCON2
SSPSTAT
REGISTERS ASSOCIATED WITH I
Synchronous Serial Port (I
Synchronous Serial Port Receive Buffer/Transmit Register
SSPIE
WCOL
SSPIF
GCEN
Bit 7
PEIF
SMP
2
C module can receive
ACKSTAT
T0CKIF
SSPOV
BCLIF
BCLIE
Bit 6
CKE
SSPEN
ACKDT
Bit 5
ADIF
ADIE
T0IF
D/A
2
C mode) Address Register
ACKEN
Bit 4
INTF
CKP
P
2
C OPERATION
SSPM3
CA4IF
CA4IE
RCEN
Bit 3
PEIE
S
15.2.4
A reset diables the SSP module and terminates the
current transfer.
T0CKIE
SSPM2
CA3IF
CA3IE
Bit 2
PEN
R/W
EFFECTS OF A RESET
SSPM1
TX2IF
TX2IE
RSEN
Bit 1
T0IE
UA
SSPM0
RC2IF
RC2IE
Bit 0
INTE
SEN
BF
1998 Microchip Technology Inc.
2
C mode.
POR, BOR
0000 0000
000- 0000
000- 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
MCLR, WDT
0000 0000
000- 0000
000- 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000

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