PIC17C752-08/CL MICROCHIP [Microchip Technology], PIC17C752-08/CL Datasheet - Page 287

• Manufacturer Part Number: PIC17C752-08/CL
• Description: High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

Figure E-6
and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identi-
cal to the start condition (SDA goes high-to-low while
FIGURE E-6:
FIGURE E-7:
FIGURE E-8:
Transfer direction of data and acknowledgment bits depends on R/W bits.
Sr
A master reads a slave immediately after the first byte.
Combined format - A master addresses a slave with a 10-bit address, then transmits
1998 Microchip Technology Inc.
For 7-bit address:
Combined format:
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
S
S
For 7-bit address:
Slave Address
S
From slave to master
From master to slave
Slave Address R/W A Data A Data A P
Slave Address R/W A Data A/A Sr
From slave to master
From master to slave
First 7 bits
Slave Address R/W A Data A Data A/A P
From slave to master
From master to slave
'1' (read)
'0' (write)
and
(write)
Figure E-7
MASTER-TRANSMITTER SEQUENCE
MASTER-RECEIVER SEQUENCE
COMBINED FORMAT
(read)
R/W A
data to this slave and reads data from this slave.
(n bytes - acknowledge)
(n bytes - acknowledge)
Slave Address
Second byte
show Master-transmitter
data transferred
data transferred
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Sr = repeated
Start Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(n bytes + acknowledge)
(read or write)
Slave Address R/W A Data A/A
A
Data
A
(write)
Data A/A
For 10-bit address:
S
For 10-bit address:
SCL is high), but occurs after a data transfer acknowl-
edge pulse (not the bus-free state). This allows a mas-
ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in
S
Slave Address
Direction of transfer
may change at this point
Slave Address
First 7 bits
First 7 bits
A master transmitter addresses a slave receiver
with a 10-bit address.
Sr Slave Address
A master transmitter addresses a slave receiver
with a 10-bit address.
Sr
Slave Address
(write)
Data A
First 7 bits
(write)
First 7 bits
P
R/W A1 Slave Address
R/W A1 Slave Address
(read)
(read)
Data
R/W A Data A
R/W A3
PIC17C7XX
Second byte
Second byte
A/A
P
Data A
DS30289A-page 287
A2
Figure
A2
Data
Data
E-8.
A
A P
P