PIC17C752-08/CL MICROCHIP [Microchip Technology], PIC17C752-08/CL Datasheet - Page 137

• Manufacturer Part Number: PIC17C752-08/CL
• Description: High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

15.1.4
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2,
cast data by the software protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON1<4>). This then would give
waveforms for SPI communication as shown in
Figure
FIGURE 15-9: SPI MODE WAVEFORM (MASTER MODE)
1998 Microchip Technology Inc.
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
15-9,
MASTER MODE
Figure
15-11, and
bit7
bit7
bit7
bit7
Figure
Figure 15-12
bit6
bit6
15-8) is to broad-
where the
bit5
bit5
bit4
bit4
MSb is transmitted first. In master mode, the SPI clock
rate (bit rate) is user programmable to be one of the fol-
lowing:
• F
• F
• F
• Timer2 output/2
This allows a maximum bit clock frequency (at 33 MHz)
of 8.25 MHz.
Figure 15-9
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
bit3
bit3
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit2
bit2
shows the waveforms for master mode.
CY
)
bit1
bit1
CY
CY
)
)
PIC17C7XX
bit0
bit0
bit0
bit0
DS30289A-page 137
Next Q4 cycle
after Q2
4 clock
modes